1. Field of the Invention
The present invention relates to a controller and a voltage detection enabling circuit thereof, especially to a voltage detection enabling circuit which determines whether or not to enable a function circuit according to a voltage parameter of a transistor.
2. Description of the Related Art
Because a power supply provided to devices inside an electronic circuit is not stable enough during the beginning when the electronic circuit is enabled, it may frequently cause erroneous operation during the period that the electronic circuit starts to operate. For avoiding the occurrence of the erroneous operation on account of unstable power supply during the beginning, a predetermined voltage value is generally set to determine whether the driving voltage is stable enough or not. The electronic circuit is then enabled only if the driving voltage reaches the predetermined voltage value.
Please refer to FIG. 1, which is the circuit diagram of under voltage lockout (UVLO) circuit of the prior art. The UVLO circuit includes a voltage divider which has resisters RD1 and RD2, a reference voltage generator VG, a comparator COM, and an AND gate AND. In which the voltage divider is coupled with a driving voltage VCC in order to generate a divided voltage signal V1.
A non-inverting input terminal of the comparator COM receives the divided voltage signal V1. An inverting input terminal of the comparator COM receives a reference voltage signal VREF generated by the reference voltage generator VG. A comparison signal CMP is generated when the divided voltage signal V1 is higher than the reference voltage signal. The AND gate AND receives the comparison signal CMP and a delay signal DELAY. When both the comparison signal CMP and the delay signal DELAY are high, an enabling signal UVLO is outputted for enabling an electronic circuit formally.
Please refer now to FIG. 2, which shows the timing diagram of the under voltage lockout circuit in FIG. 1. After the circuit is enabled, the driving voltage VCC increases, so the divided voltage signal V1 increases accordingly. Because the reference voltage generator VG is also driven by the driving voltage VCC, the reference voltage generator VG starts to generate the reference voltage signal VREF when the driving voltage VCC increases and reaches the potential level which is capable to drive the reference voltage generator VG. At time point t1, the reference voltage generator VG starts to generate the reference voltage signal VREF. However, the reference voltage signal VREF reaches a steady value only when the driving voltage VCC increases and reaches a higher potential level.
As the time the reference voltage generator VG is driven and enabled, the comparator COM is also enabled. At the moment. Because the reference voltage signal VREF is lower then the divided voltage signal V1 during the beginning of the reference voltage generator VG, the potential of outputted comparison signal CMP is high. At time point t3, the potential level of the reference voltage signal VREF rises and becomes higher than the divided voltage signal V1, the comparator COM stops outputting the comparison signal CMP since the potential of the comparison signal CMP is low.
For avoiding the comparator COM from performing wrong comparison because of the unstable reference voltage signal VREF during the beginning of the reference voltage generator VG, a delay signal DELAY is provided. The delay signal DELAY is set to generate a delay time Td after the circuit is enabled.
The delay signal DELAY is adopted to avoid the erroneous judgment. However, the rising speed of driving voltage VCC in different power supply is different, the comparison may still err for the slow rising speed of the driving voltage VCC. As shown in the present case, the time point t2 of the delay signal DELAY generating comes before the time point t3, thus during the period between t2 and t3, the enabling signal UVLO may still provide error output. Until the time point t4, the divided voltage signal V1 becomes higher than the stable reference voltage signal VREF again, so the enabling signal UVLO is outputted correctly.
As described above, the prior under voltage lockout circuit may still possibly make wrong determination, trigger error actions, and further cause circuit damage. Therefore, the problem is what should be overcome.